Many multiple wireline communication systems, such as DSL (digital subscribe line) systems and gigabit Ethernet systems suffer from echo and crosstalks. Echo and NEXT (near-end crosstalk) cancellers are widely used to counter the effect of echo and NEXT noise. In 10 Gigabit Ethernet over copper (10GBase-T) system, full duplex baseband transmission is performaned over four pairs of UTP (unshield twisted pair). Each received signal is corrupted by echo from its own transmitter and NEXT interferences from three adjacent transmitters. To meet the desired throughput and target BER (10−12) requirements, echo and NEXT noise cancellation are expected to be about 55 dB and 40 dB, respectively.
The typical way to perform echo and NEXT noise cancellation is using finite impulse response (FIR) filters in digital domain, where the replica of the echo and NEXT estimated by the FIR filters is subtracted from the received noisy signals. This straightforward approach, however, will have a significant complexity if the size of the FIR filters is large and thus leads to large power and silicon area. In the 10GBase-T transceivers, 16 long FIR filters need to be implemented for noise cancellation. Due to the extreme high symbol rate (such as 800 Mega Baud required for 10Gbase-T) and high noise cancellation level requirement, each FIR-filter based canceller can be of several hundred taps, and the number of total taps is around 7000. Implementing those filters at such a high speed requires a significant amount of power. Therefore reducing the power consumption of these FIR filters is important for a successful DSP transceiver design.
How to design low power echo and NEXT cancellers for 10GBase-T transceivers is a challenging task. It is apparent in the industry that the FIR techniques used in 1000 BASE-T solutions, if implemented in a straightforward way, would result in a complexity increase on the order of 45× over 1000 BASE-T. The high degree of cancellation required at these speeds also makes all-analog cancellation difficult, since both high bandwidth and high power of adaptive analog filters are required if feasible. By using DFT transformation, approximate complexity saving can be 90% (See, e.g., Sanjay Kasturia and Jose Tellado, “Lower Complexity Architectures for Implementing 10GBT XTalk Cancellers and Equalizers FIRs”, 10GBase-T Study Group Meeting, http://www.ieee802.org/3/10GBT/public/sep03/kasturia—1—0903.pdf, September 2003). However, new issues such as block processing latency, increased memory and increased precision, associated with this technique make it unacceptable for the 10GBase-T application. Because of the inherent time-varying and randomness of the channel impulse responses, simple techniques to extend the length of the impulse response cancelled, such as continuous-time analog filters or infinite impulse response (IIR) digital filters are not flexible solutions. Methods proposed to exploit the sparsity of the echo and NEXT impulse responses are also not trivial as accurate channel estimates are needed before those significant taps with large magnitude can be identified. The problem becomes even worse by introducing Tomlinson-Harashima precoding (TH precoding) in 10GBase-T as the inputs to echo and NEXT cancellers are no longer simple PAM-M symbols but numbers uniformly distributed on [−M, M). Hence, the wordlength of the inputs for echo and NEXT cancellers could be as long as 10 bits, which further increases the complexity and cost of echo and NEXT cancellers (See, e.g., G. Zimmerman, “Downside of TH Precoding”, 10GBase-T Study Group Meeting, http://www.ieee802.org/3/an/public/may04/zimmerman—1—0504.pdf, May, 2004).
What is needed is a method for designing efficient echo and NEXT cancellers that achieve minimal power consumption and area costs by reducing word-length requirements.